31 | 0h | RO | Detected Parity Error (DPE) Not implemented. Hardwired to 0. |
30 | 0h | RO | Signaled System Error (SSE) Not implemented. Hardwired to 0. |
29 | 0h | RW/1C/V | Received Master Abort (RMA) This bit must be set by a master device whenever its transaction \t\t(except for Special Cycle) is completed with Unsupported Request Completion \t\tStatus (a.k.a. Master-Abort). All master \t\tdevices must implement this bit. |
28 | 0h | RW/1C/V | Received Target Abort (RTA) This bit must be set by a master device whenever its transaction is \t\tcompleted with Completer Abort Completion Status (a.k.a. Target-Abort). \t\tAll master devices must implement this bit. |
27 | 0h | RW/1C/V | Signaled Target Abort (STA) This bit must be set by a target device whenever it completes a Posted or Non-Posted \t\ttransaction with a Completer Abort (a.k.a. Target-Abort) error. Devices that \t\twill never signal Completer Abort (a.k.a. Target-Abort) do not need to implement this bit. |
26:25 | 0h | RO | Devsel Timing (DEVT) These bits encode the timing of DEVSEL#. \t\tThere are three allowable timings for assertion of DEVSEL# as described below: \t\t 00b: fast; \t\t 01b: medium; \t\t 10b: slow; \t\t 11b: reserved. \t\t These bits are read-only and must indicate the slowest time \t\tthat a device asserts DEVSEL# for any bus command except \t\tConfiguration Read and Configuration Write. \t\t
\t\t Hardwired to 00b. |
24 | 0h | RO | Master Data Parity Error (MDPE) Not implemented. Hardwired to 0. |
23 | 1h | RO | Fast Back To Back Capable (FBTBC) This bit indicates whether or not the target is \t\tcapable of accepting fast back-to-back transactions when the \t\ttransactions are not to the same agent. This bit can be set to 1 if the \t\tdevice can accept these transactions and must be set to 0 otherwise. \t\t
\t\t Hardwired to 1. |
22 | 0h | RO | Reserved (RSVD3) Reserved (RSVD) |
21 | 1h | RO | 66 Mhz Capable (MCAP) This bit indicates whether or not this device is \t\tcapable of running at 66 MHz. \t\t A value of 0 indicates 33 MHz. \t\t A value of 1 indicates that the device is 66 MHz capable. \t\t
\t\t Hardwired to 1. |
20 | 1h | RO | Capabilities List (CAPL) This optional read-only bit indicates whether or not this device \t\timplements the pointer for a New Capabilities linked list at offset 34h. \t\tA value of zero indicates that no New Capabilities linked list is \t\tavailable. A value of one indicates that the value read at offset 34h is \t\ta pointer in Configuration Space to a linked list of new capabilities. |
19 | 0h | RO | Interrupt Status (INTS) This read-only bit reflects the state of the interrupt in the \t\tdevice/function. Only when the Interrupt Disable bit in the command \t\tregister is a 0 and this Interrupt Status bit is a 1, will the \t\tdevice's/function's INTx# signal be asserted. Setting the Interrupt \t\tDisable bit to a 1 has no effect on the state of this bit. \t\t Read-only and hardwired to 0 for a device that does NOT support \t\tpin-based interrupt. |
18:16 | 0h | RO | Reserved (RSVD2) |
15:11 | 0h | RO | Reserved (RSVD1) |
10 | 0h | RW | Interrupt Disable (INTD) This bit disables the device/function from asserting INTx#. A value of 0 enables the assertion of its INTx# signal. A value of 1 disables the assertion of its INTx# signal. This bit's state after RST# is 0. |
9 | 0h | RO | Fast Back To Back Enable (FBTBEN) Not implemented. Hardwired to 0. |
8 | 0h | RO | System Error Enable (SERREN) Not implemented. Hardwired to 0. |
7 | 0h | RO | Reserved (RSVD0) |
6 | 0h | RO | Parity Error Response (PERRR) Not implemented. Hardwired to 0. |
5 | 0h | RO | VGA Palette Snoop (VGAPS) Not implemented. Hardwired to 0. |
4 | 0h | RO | Memory Write And Invalidate Enable (MWRIEN) Not implemented. Hardwired to 0. |
3 | 0h | RO | Special Cycles (SPCYC) Not implemented. Hardwired to 0. |
2 | 0h | RW | Bus Master Enable (BME) Controls the ability of a PCI device \t\tto issue Memory and I/O Read/Write Requests, and \t\tthe ability of a PCI bridge to forward Memory and I/O \t\tRead/Write Requests in the Upstream direction. \t\t
\t\t Devices: \t\t When this bit is Set, the PCI device function is allowed to \t\tissue Memory or I/O Requests. \t\tWhen this bit is Clear, the PCI device function is not allowed \t\tto issue any Memory or I/O Requests. \t\t Note that as MSI/MSI-X interrupt Messages are in-band memory \t\twrites, setting the Bus Master Enable bit to 0b disables \t\tMSI/MSI-X interrupt Messages as well. \t\t Requests other than Memory or I/O Requests are not controlled \t\tby this bit. \t\t Default value of this bit is 0b. \t\t This bit is hardwired to 0b if a PCI device function does not generate \t\tMemory or I/O Requests. \t\t
\t\t Bridges: \t\t This bit controls forwarding of Memory or I/O Requests by a \t\tbridge in the Upstream direction. When this bit is \t\t0b, Memory and I/O Requests received at the \t\tDownstream side of a bridge must be handled as \t\tUnsupported Requests (UR), and for Non-Posted Requests a \t\tCompletion with UR completion status must be returned. This \t\tbit does not affect forwarding of Completions in either the \t\tUpstream or Downstream direction. \t\tThe forwarding of Requests other than Memory or I/O Requests \t\tis not controlled by this bit. \t\t Default value of this bit is 0b. |
1 | 0h | RW | Memory Space Enable (MSE) Controls a device's response to Memory Space accesses. A value of \t\t0 disables the device response. A value of 1 allows the device to \t\trespond to Memory Space accesses. State after RST# is 0. |
0 | 0h | RW | IO Space Enable (IOSE) Controls a device's response to I/O Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to I/O Space accesses. State after RST# is 0. |