Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
PCI Command & Status Register (PCICMD_STS) – Offset 4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RW/V | Detected Parity Error (DPE) [BR]0 = No parity error detected.[BR] |
30 | 0h | RW/V | Signaled System Error (SSE) [BR]0 = No system error signaled.[BR] |
29 | 0h | RW/V | Received Master Abort (RMA) [BR]0 = Root port has not received a completion with unsupported request status from the backbone.[BR] |
28 | 0h | RW/V | Received Target Abort (RTA) [BR]0 = Root port has not received a completion with completer abort from the backbone.[BR] |
27 | 0h | RW/V | Signaled Target Abort (STA) [BR]0 = No target abort received.[BR] |
26:25 | 0h | RW/V | DEVSEL# Timing Status (DEV_STS) Hardwired to 0. |
24 | 0h | RW/V | Master Data Parity Error Detected (DPED) [BR]0 = No data parity error received.[BR] |
23 | 0h | RW/V | Fast Back to Back Capable (FB2BC) Hardwired to 0. |
22 | 0h | RO | Reserved |
21 | 0h | RW/V | 66 MHz Capable (MHZ_66_CPBL) Hardwired to 0. |
20 | 1h | RW/V | Capabilities List (NEW_CPBL) Hardwired to 1. Indicates the presence of a capabilities list. |
19 | 0h | RW/V | Interrupt Status (INT_STAT) Indicates status of hot-plug and power management interrupts on the root |
18:11 | 0h | RO | Reserved |
10 | 0h | RW | Interrupt Disable (INT_DIS) This disables pin-based INTx# interrupts on enabled hot-plug and power |
9 | 0h | RW/V | Fast Back to Back Enable (FBE) Hardwired to 0. |
8 | 0h | RW | SERR# Enable (SEE) [BR]0 = Disable[BR] |
7 | 0h | RW/V | Wait Cycle Control (WCC) Hardwired to 0. |
6 | 0h | RW | Parity Error Response (PER) [BR]0 = Disable.[BR] |
5 | 0h | RW/V | Palette Snoop Enable (PSE) Hardwired to 0. |
4 | 0h | RW/V | Postable Memory Write Enable (PMWE) Hardwired to 0. |
3 | 0h | RW/V | Special Cycle Enable (SCE) Hardwired to 0. |
2 | 0h | RW | Bus Master Enable (BME) [BR]0 = Disable. All cycles from the device are master aborted[BR] |
1 | 0h | RW | Memory Space Enable (MSE) [BR] |
0 | 0h | RW/V | I/O Space Enable (IOSE) This bit controls access to the I/O space registers.[BR] |