Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
TCO1_STS Register (TSTS1) – Offset 4
Unless otherwise indicated, these bits are sticky and are cleared by writing a 1 to the corresponding bit position.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:14 | 0h | RO | Reserved (RSVD) Reserved |
13 | 0h | RO | TCO Slave Select (TCO_SLVSEL) This register bit indicates the value of TCO Slave Select Soft Strap. |
12 | 0h | RW/1C | CPUSERR_STS (CPUSERR_STS) This bit is set to 1 if the CPU complex sends a DMI special cycle message indicating that it wants to cause an SERR#. The software must read the MCH to find out why it wanted the SERR#. Software must write a 1 back to this bit to clear it. |
11 | 0h | RO | Reserved |
10 | 0h | RW/1C | CPUSMI_STS (CPUSMI_STS) This bit is set to 1 if the Compute tile indicates that it wants to cause an SMI. The software must read the Compute tile to find out why it wanted the SMI. Software must write a 1 back to this bit to clear it. |
9 | 0h | RW/1C | CPUSCI_STS (CPUSCI_STS) This bit is set to 1 if the Compute tile indicates that it wants to cause an SCI. The software must read the Compute tile to find out why it wanted the SCI. Software must write a 1 back to this bit to clear it. |
8 | 0h | RW/1C | BIOSWR_STS (BIOSWR_STS) Intel processor sets this bit to 1 and generates and SMI# to indicate an unwanted attempt to write to the BIOS. This occurs when either: a) The WP bit is changed from 0 to 1 and the LE bit is also set, or b) any write is attempted to the BIOS and the WP bit is also set. |
7 | 0h | RW/1C | NEWCENTURY_STS (NEWCENTURY_STS) This bit will be set when the year rolls over from 1999 to 2000. If the bit is already 1, it will remain 1. This bit can be cleared either by software writing a 1 back to the bit position, or by RTCRST# going active. When this bit is set, an SMI# will be generated. However, this will not be a wake event (i.e. if the system is in a sleeping state when the NEWCENTURY_STS bit is set, the system will not wake up). |
6:4 | 0h | RO | Reserved |
3 | 0h | RW/1C | TIMEOUT (TIMEOUT) Bit set to 1 to indicate that the SMI was caused by TCO timer reaching 0. Note: The SMI handler should clear this bit to prevent an immediate re-entry to the SMI handler. |
2 | 0h | RW/1C | TCO_INT_STS (TCO_INT_STS) Bit set to 1 when SMI handler caused the interrupt by writing to the TCO_DAT_OUT register. |
1 | 0h | RW/1C | OS_TCO_SMI (OS_TCO_SMI) Bit set to 1 when OS code caused an SMI# by writing to the TCO_DAT_IN register. |
0 | 0h | RO/V | NMI2SMI_STS (NMI2SMI_STS) This read-only bit is set when an SMI# occurs because an event occurred that would otherwise have caused an NMI. The NMI2SMI_STS bit is not sticky bit. Writes to this bit have no effect. |