Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Input / Output Processing Pipes Link Connection on Format (IPPLC4FMT) – Offset 984
This register specifies the audio format on the link connection end of the processing pipe.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15 | 0h | RO | Reserved (RSVD3) This is a Reserved Register |
14 | 0h | RW | Sample Base Rate (BASE) 0=48 kHz1=44.1 kHz |
13:11 | 0h | RW | Sample Base Rate Multiple (MULT) 000=48 kHz/44.1 kHz or less001=x2 (96 kHz, 88.2 kHz, 32 kHz)010=x3 (144 kHz)011=x4 (192 kHz, 176.4 kHz)100-111=Reserved |
10:8 | 0h | RW | Sample Base Rate Divisor (DIV) 000=Divide by 1 (48 kHz, 44.1 kHz)001=Divide by 2 (24 kHz, 22.05 kHz)010=Divide by 3 (16 kHz, 32 kHz)011=Divide by 4 (11.025 kHz)100=Divide by 5 (9.6 kHz)101=Divide by 6 (8 kHz)110=Divide by 7111=Divide by 8 (6 kHz) |
7 | 0h | RO | Reserved (RSVD4) This is a Reserved Register |
6:4 | 0h | RW | Bits per Sample (BITS) 000=8 bits. The data will be packed in memory in 8-bit containers on 16-bit boundaries001=16 bits. The data will be packed in memory in 16-bit containers on 16-bit boundaries010=20 bits. The data will be packed in memory in 32-bit containers on 32- bit boundaries011=24 bits. The data will be packed in memory in 32-bit containers on 32- bit boundaries100=32 bits. The data will be packed in memory in 32-bit containers on 32- bit boundaries101-111=Reserved |
3:0 | 0h | RW | Number of Channels (CHAN) Number of channels in each frame of the stream:0000=10001=21111=16 |