Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
PCI Express Capabilities Register (EXPCAP) – Offset 82
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:14 | 0h | RO | Reserved (RSVD) Reserved |
13:9 | 0h | RO | Interrupt Message Number (IMN) This field indicates the interrupt message number that is generated from the PCI Express port. When there is more than one MSI interrupt number, this register is required to contain the offset between the base Message Data and the MSI Message that is generated when the status bits in the slot status register or root port status registers are set. The chipset is required to update this field if the number of MSI messages change |
8 | 0h | RO | Slot Implemented (SI) Hardwired to 0. This bit is not applicable to Endpoint. |
7:4 | 0h | RO | Device/Port Type (DT) Defined encodings are: |
3:0 | 1h | RO | Capability Version (CV) Compliant to PCIe base specification 1.0.a |