Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Power Control Enable (PCE) – Offset d2
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7:6 | 0h | RO | Reserved (RSVD0) This is a Reserved Register |
5 | 1h | RW | Hardware Autonomous Enable (HAE) If set, then the IP may request a PG whenever it is idle. |
4 | 0h | RO | Reserved (RSVD1) This is a Reserved Register |
3 | 1h | RW/L | Sleep Enable (SE) If clear, then the IP will never assert Sleep. If set, then the IP may assert Sleep during PGing. |
2 | 0h | RW | D3-Hot Enable (D3HE) If set, then IP will PG when idle and the PCS.PS register in the IP =11. |
1 | 0h | RW | I3 Enable (I3E) If set, then the IP will PG when idle and the D0i3 register (D0I3C.I3 = 1) is set.NOTE: If bits [2:1] = 11, then the IP would PG whenever either the D3 register or the D0i3 register is set. |
0 | 0h | RW | PMC Request Enable (PMCRE) If set, then the IP will power gate (PG) when idle and the PMC requests power gating. |