Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
eSPI IO Routing Enables for ESPI CS2 (ESPI_IORE_EXT[2]) – Offset 200
This register is used to route fixed I/O transactions from the Host to the targeted device over the Peripheral Channel on the eSPI bus.
This register is locked in a configuration where targeted device is disabled. All writes to this register must be dropped and reads to this register must return the default (reset) values.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:15 | 0h | RO | Reserved |
14 | 0h | RW/V | Debug Port CS# Routing Enable (DPRE) Enables routing of I/O locations 80h, 84h-86h, 88h, 8Ch-8Eh, 90h, 94h-96h, 98h, 9Ch-9Eh to eSPI CS#. |
13 | 0h | RW/V | Microcontroller #2 CS# Routing Enable (MRE2) Enables routing of I/O locations 4Eh and 4Fh to eSPI CS#. |
12 | 0h | RW/V | SuperI/O CS# Routing Enable (SRE) Enables routing of I/O locations 2Eh and 2Fh to eSPI CS#. |
11 | 0h | RW/V | Microcontroller #1 CS# Routing Enable (MRE1) Enables routing of I/O locations 62h and 66h to eSPI CS#. |
10 | 0h | RW/V | Keyboard CS# Routing Enable (KRE) Enables routing of the keyboard I/O locations 60h and 64h to eSPI CS#. |
9 | 0h | RW/V | High Gameport CS# Routing Enable (HGRE) Enables routing of the I/O locations 208h to 20Fh to eSPI CS#. |
8 | 0h | RW/V | Low Gameport CS# Routing Enable (LGRE) Enables routing of the I/O locations 200h to 207h to eSPI CS#. |
7:4 | 0h | RO | Reserved |
3 | 0h | RW/V | Floppy Drive CS# Routing Enable (FDRE) Enables routing of the FDD range to eSPI CS#. Range is selected by LIOD.FDE. |
2 | 0h | RW/V | Parallel Port CS# Routing Enable (PPRE) Enables routing of the LPT range to eSPI CS#. Range is selected by LIOD.LPT. |
1 | 0h | RW/V | Com Port B CS# Routing Enable (CBRE) Enables routing of the COMB range to eSPI CS#. Range is selected by LIOD.CB. |
0 | 0h | RW/V | Com Port A CS# Routing Enable (CARE) Enables routing of the COMA range to eSPI CS#. Range is selected by LIOD.CA. |