Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG SPI_CS_CONTROL (SPI_CS_CONTROL) – Offset 224
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RO | Reserved |
15 | 1h | RW | cs3_polarity (cs3_polarity) This Bit selects the Inactive/Idle polarity of SPI CS3 Signal. The steering logic will ensure |
14 | 1h | RW | cs2_polarity (cs2_polarity) This Bit selects the Inactive/Idle polarity of SPI CS2 Signal. The steering logic will ensure |
13 | 1h | RW | cs1_polarity (cs1_polarity) This Bit selects the Inactive/Idle polarity of SPI CS1 Signal. The steering logic will ensure |
12 | 1h | RW | cs0_polarity (cs0_polarity) This Bit selects the Inactive/Idle polarity of SPI CS0 Signal. The steering logic will ensure |
11:10 | 0h | RO | Reserved |
9:8 | 0h | RW | cs1_output_sel (cs1_output_sel) These Bits select which SPI CS Signal is to be driven by the SSP Frame (CS). |
7:2 | 0h | RO | Reserved |
1 | 0h | RW | cs_state (cs_state) Manual SW control of SPI Chip Select (CS) |
0 | 0h | RW | cs_mode (cs_mode) SPI Chip Select Mode Section. |