Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
xDCI (USB Device Control) PCI Configuration (D20:F1) Registers
The following registers are at Device 20:Function 1.
Offset | Size (Bytes) | Register Name (Register Symbol) | Scope | Default Value |
---|---|---|---|---|
0h | 4 | Package | XXXX8086h | |
4h | 4 | Package | 00100000h | |
8h | 4 | Package | 0C03FEXXh | |
ch | 4 | Package | 00000000h | |
10h | 4 | Package | 00000004h | |
14h | 4 | Package | 00000000h | |
18h | 4 | Package | 00000004h | |
1ch | 4 | Package | 00000000h | |
2ch | 4 | Package | 00000000h | |
30h | 4 | Package | 00000000h | |
34h | 4 | Package | 00000080h | |
3ch | 4 | Package | 00000100h | |
80h | 4 | Package | 48039001h | |
84h | 4 | Power Management Control And Status Register (PMECTRLSTATUS) | Package | 00000008h |
90h | 4 | Package | F0140009h | |
94h | 4 | Vendor Specific Extended Capability (DEVID_VEND_SPECIFIC_REG) | Package | 01400010h |
98h | 4 | Software LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG) | Package | 00000000h |
9ch | 4 | Package | 010F8301h | |
a0h | 4 | D0i3 And Power Control Enable (D0I3_MAX_POW_LAT_PG_CONFIG) | Package | 00080800h |