Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG CTL_HI1 (CTL_HI1) – Offset 874
This register contains fields that control the DMA transfer. The CTL_HI register is part of the block descriptor (linked
list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when
block chaining is enabled.If status write-back is enabled, CTL_HI is written to then control registers location of the LLI
in system memory at the end of the block transfer.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:29 | 0h | RW | CH_CLASS (CH_CLASS) Channel Class. A Class of (N_CHNLS-1) is the highest priority, and 0 is the lowest. |
28:18 | 0h | RO | Reserved |
17 | 0h | RW | DONE (DONE) If status write-back is enabled, the upper word of the control register, CTL_HIn, is |
16:0 | 0h | RW | BLOCK_TS (BLOCK_TS) Block Transfer Size (in Bytes). |