Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Device Generic Command Register (DGCMD) – Offset c714
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RO | Reserved |
15:12 | 0h | RO | Command Status (CMDSTATUS) 1: CmdErr – Indicates that the device controller encountered an error while processing the command. |
11 | 0h | RO | Reserved |
10 | 0h | NA | Command Active (CMDACT) The software sets this bit to 1 to enable the device controller to execute the generic command. |
9 | 0h | RO | Reserved |
8 | 0h | RW | Command Interrupt on Complete (CMDIOC) When this bit is set, the device controller issues a Generic Command Completion event after executing the command. Note that this interrupt is mapped to DCFG.IntrNum. |
7:0 | 0h | RW | Command Type (CMDTYP) Specifies the type of command the software driver is requesting the core to perform: |