Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Interrupter Management (IMAN0) – Offset 2020
The register listed in this section is at offset 2020h for IMAN0.
There are a total of 8 IMAN registers at the following offsets:
IMAN0: at offset 2020h
IMAN1: at offset 2040h
IMAN2: at offset 2060h
.....
IMAN6: at offset 20E0h
IMAN7; at offset 2100h
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:2 | 0h | RO | Rsvd1 (RSVD1) Reserved |
1 | 0h | RW | Interrupt Enable (IE) This flag specifies whether the Interrupter is capable of generating an interrupt. |
0 | 0h | RW/1C | Interrupt Pending (IP) 0 = No interrupt is pending for the Interrupter. |