31:30 | 0h | RO | CFIO Pad Configuration I2CEN (CFIOPADCFG_I2CEN) See CFIO HIP Interface for details on these control bit descriptions. These may be duplicates in the family settings register since these can be either Family or Pad signals and this is SoC specific. The superset is described here and register bits are implemented only for those configurations that are pad specific. Bits that aren't implemented or output of the CFIO are read only. \t\t\t |
29 | 0h | RW | CFIO Pad Configuration CSEN (CFIOPADCFG_CSEN) See CFIO HIP Interface for details on these control bit descriptions. These may be duplicates in the family settings register since these can be either Family or Pad signals and this is SoC specific. The superset is described here and register bits are implemented only for those configurations that are pad specific. Bits that aren't implemented or output of the CFIO are read only. \t\t\t |
28 | 0h | RO | CFIO Pad Configuration PARKMODEEN_B (CFIOPADCFG_PARKMODEEN_B) See CFIO HIP Interface for details on these control bit descriptions. These may be duplicates in the family settings register since these can be either Family or Pad signals and this is SoC specific. The superset is described here and register bits are implemented only for those configurations that are pad specific. Bits that aren't implemented or output of the CFIO are read only. \t\t\t |
27:26 | 0h | RO | CFIO Pad Configuration HYSCTL (CFIOPADCFG_HYSCTL) See CFIO HIP Interface for details on these control bit descriptions. These may be duplicates in the family settings register since these can be either Family or Pad signals and this is SoC specific. The superset is described here and register bits are implemented only for those configurations that are pad specific. Bits that aren't implemented or output of the CFIO are read only. \t\t\t |
25 | 0h | RO | CFIO Pad Configuration PADTOL (CFIOPADCFG_PADTOL) See CFIO HIP Interface for details on these control bit descriptions. These may be duplicates in the family settings register since these can be either Family or Pad signals and this is SoC specific. The superset is described here and register bits are implemented only for those configurations that are pad specific. Bits that aren't implemented or output of the CFIO are read only. \t\t\t |
24:22 | 0h | RO | CFIO Pad Configuration STRSEL (CFIOPADCFG_STRSEL) See CFIO HIP Interface for details on these control bit descriptions. These may be duplicates in the family settings register since these can be either Family or Pad signals and this is SoC specific. The superset is described here and register bits are implemented only for those configurations that are pad specific. Bits that aren't implemented or output of the CFIO are read only. \t\t\t |
21 | 0h | RO | CFIO Pad Configuration HSMODE (CFIOPADCFG_HSMODE) See CFIO HIP Interface for details on these control bit descriptions. These may be duplicates in the family settings register since these can be either Family or Pad signals and this is SoC specific. The superset is described here and register bits are implemented only for those configurations that are pad specific. Bits that aren't implemented or output of the CFIO are read only. \t\t\t |
20 | 0h | RO | CFIO Pad Configuration ODTUPDN (CFIOPADCFG_ODTUPDN) See CFIO HIP Interface for details on these control bit descriptions. These may be duplicates in the family settings register since these can be either Family or Pad signals and this is SoC specific. The superset is described here and register bits are implemented only for those configurations that are pad specific. Bits that aren't implemented or output of the CFIO are read only. \t\t\t |
19 | 0h | RO | CFIO Pad Configuration ODTEN (CFIOPADCFG_ODTEN) See CFIO HIP Interface for details on these control bit descriptions. These may be duplicates in the family settings register since these can be either Family or Pad signals and this is SoC specific. The superset is described here and register bits are implemented only for those configurations that are pad specific. Bits that aren't implemented or output of the CFIO are read only. \t\t\t |
18 | 0h | RO | CFIO Pad Configuration ANALOGMUXEN (CFIOPADCFG_ANALOGMUXEN) See CFIO HIP Interface for details on these control bit descriptions. These may be duplicates in the family settings register since these can be either Family or Pad signals and this is SoC specific. The superset is described here and register bits are implemented only for those configurations that are pad specific. Bits that aren't implemented or output of the CFIO are read only. \t\t\t |
17:14 | 0h | RW | IO Standby State (IOSSTATE) Same description as IOSSTATE bits in PAD_CFG_DW1_xxgpp_v_0. |
13:10 | 0h | RW | Termination (TERM) Same description as TERM bits in PAD_CFG_DW1_xxgpp_v_0. |
9:8 | 0h | RW | IO Standby Termination (IOSTERM) Same description as IOSTERM bits in PAD_CFG_DW1_xxgpp_v_0. |
7:0 | 1ch | RO | Interrupt Select (INTSEL) Same description as INTSEL bits in PAD_CFG_DW1_xxgpp_v_0. |