High Precision Event Timer (HPET) MMIO Registers

Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers

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ID 795260

Date 12/14/2023

Version 001

Public

The timer registers are memory mapped directly (rather than indexed) to allow the processor to access each register without having to use an index register. This ensures accesses are safe for multi-threaded environments. The timer register space is 1024 bytes. The registers are generally aligned on 64-bit boundaries.
There are 4 possible memory address ranges beginning at 1) FED0_0000h, 2) FED0_1000h, 3) FED0_2000h, 4) FED0_3000h. The choice of address range should be selected by assigning the High Performance Event Timer Configuration (HPTC) register fields in the configuration space of the Primary to Sideband Bridge. All registers are implemented in the Primary power well, and all bits are reset by PLTRST#. Reads to reserved registers or bits will return a value of 0.
Behavorial Rules:
1. Software can read or write the various bytes in these registers using 32-bit or 64-bit accesses. Software must not attempt to read or write across register boundaries. For
example, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh.
Any accesses to these offsets will result in an unexpected behavior, and may result in a master abort. However, these accesses should not result in system hangs. 64-bit accesses can only be to x0h and must not cross 64-bit boundaries.
2. Software should not write to read-only registers.
3. Software should not expect any particular or consistent value when reading reserved registers or bits.

Summary of Bus: (), Device: (), Function: (), Type: (MEM)

Offset	Size (Bytes)	Register Name (Register Symbol)	Scope	Default Value
0h	8	General Capabilities and ID Register (GEN_CAP_ID)	Package	027BC86B8086A701h
10h	8	General Config Register (GEN_CFG)	Package	0000000000000000h
20h	8	General Interrupt Status Register (GEN_INT_STS)	Package	0000000000000000h
f0h	8	Main Counter Value (MAIN_CNTR)	Package	0000000000000000h
100h	8	Timer 0 Config and Capabilities (TMR0_CNF_CAP)	Package	00F0000000008030h
108h	8	Timer 0 Comparator Value (TMR0_CMP_VAL)	Package	FFFFFFFFFFFFFFFFh
110h	8	Timer 0 FSB Interrupt Rout Register (TMR0_FSB_INT_ROUT)	Package	0000000000000000h
120h	8	Timer 1 Config and Capabilities (TMR1_CNF_CAP)	Package	0000000000000000h
128h	8	Timer 1 Comparator Value (TMR1_CMP_VAL)	Package	0000000000000000h
130h	8	Timer 1 FSB Interrupt Rout Register (TMR1_FSB_INT_ROUT)	Package	0000000000000000h
140h	8	Timer 2 Config and Capabilities (TMR2_CNF_CAP)	Package	0000000000000000h
148h	8	Timer 2 Comparator Value (TMR2_CMP_VAL)	Package	0000000000000000h
150h	8	Timer 2 FSB Interrupt Rout Register (TMR2_FSB_INT_ROUT)	Package	0000000000000000h
160h	8	Timer 3 Config and Capabilities (TMR3_CNF_CAP)	Package	0000000000000000h
168h	8	Timer 3 Comparator Value (TMR3_CMP_VAL)	Package	0000000000000000h
170h	8	Timer 3 FSB Interrupt Rout Register (TMR3_FSB_INT_ROUT)	Package	0000000000000000h
180h	8	Timer 4 Config and Capabilities (TMR4_CNF_CAP)	Package	0000000000000000h
188h	8	Timer 4 Comparator Value (TMR4_CMP_VAL)	Package	0000000000000000h
190h	8	Timer 4 FSB Interrupt Rout Register (TMR4_FSB_INT_ROUT)	Package	0000000000000000h
1a0h	8	Timer 5 Config and Capabilities (TMR5_CNF_CAP)	Package	0000000000000000h
1a8h	8	Timer 5 Comparator Value (TMR5_CMP_VAL)	Package	0000000000000000h
1b0h	8	Timer 5 FSB Interrupt Rout Register (TMR5_FSB_INT_ROUT)	Package	0000000000000000h
1c0h	8	Timer 6 Config and Capabilities (TMR6_CNF_CAP)	Package	0000000000000000h
1c8h	8	Timer 6 Comparator Value (TMR6_CMP_VAL)	Package	0000000000000000h
1d0h	8	Timer 6 FSB Interrupt Rout Register (TMR6_FSB_INT_ROUT)	Package	0000000000000000h
1e0h	8	Timer 7 Config and Capabilities (TMR7_CNF_CAP)	Package	0000000000000000h
1e8h	8	Timer 7 Comparator Value (TMR7_CMP_VAL)	Package	0000000000000000h
1f0h	8	Timer 7 FSB Interrupt Rout Register (TMR7_FSB_INT_ROUT)	Package	0000000000000000h