Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Status And Command (IDE_HOST_STS_CMD) – Offset 4
This register contins the PCI status and command registers.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RO | Detected Parity Error (DPE) Not implemented. Hardwired to 0. |
30 | 0h | RO | Signaled System Error (SSE) Not implemented. Hardwired to 0. |
29 | 0h | RW/1C/V | Received Master Abort (RMA) This bit must be set by a master device whenever its transaction (except for Special Cycle) is completed with Unsupported Request Completion Status (a.k.a. Master-Abort). |
28 | 0h | RW/1C/V | Received Target Abort (RTA) This bit must be set by a master device whenever its transaction is |
27 | 0h | RW/1C/V | Signaled Target Abort (STA) This bit must be set by a target device whenever it completes a Posted or Non-Posted transaction with a Completer Abort (a.k.a. Target-Abort) error. Devices that will never signal Completer Abort (a.k.a. Target-Abort) do not need to implement this bit. |
26:25 | 0h | RO | Devsel Timing (DEVT) These bits encode the timing of DEVSEL#. |
24 | 0h | RO | Master Data Parity Error (MDPE) Not implemented. Hardwired to 0. |
23 | 1h | RO | Fast Back To Back Capable (FBTBC) This bit indicates whether or not the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to 1 if the device can accept these transactions and must be set to 0 otherwise. |
22 | 0h | RO | Reserved |
21 | 1h | RO | 66 Mhz Capable (MCAP) This bit indicates whether or not this device is capable of running at 66 MHz. |
20 | 1h | RO | Capabilities List (CAPL) This optional read-only bit indicates whether or not this device |
19 | 0h | RO | Interrupt Status (INTS) This read-only bit reflects the state of the interrupt in the device/function. Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1, will the device's/function's INTx# signal be asserted. Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. |
18:11 | 0h | RO | Reserved |
10 | 0h | RW | Interrupt Disable (INTD) This bit disables the device/function from asserting INTx#. |
9 | 0h | RO | Fast Back To Back Enable (FBTBEN) Not implemented. Hardwired to 0. |
8 | 0h | RO | System Error Enable (SERREN) Not implemented. Hardwired to 0. |
7 | 0h | RO | Reserved |
6 | 0h | RO | Parity Error Response (PERRR) Not implemented. Hardwired to 0. |
5 | 0h | RO | VGA Palette Snoop (VGAPS) Not implemented. Hardwired to 0. |
4 | 0h | RO | Memory Write And Invalidate Enable (MWRIEN) Not implemented. Hardwired to 0. |
3 | 0h | RO | Special Cycles (SPCYC) Not implemented. Hardwired to 0. |
2 | 0h | RW | Bus Master Enable (BME) Controls the ability of a PCI device to issue Memory and I/O Read/Write Requests, and the ability of a PCI bridge to forward Memory and I/O Read/Write Requests in the Upstream direction. |
1 | 0h | RO | Memory Space Enable (MSE) Controls a device's response to Memory Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to Memory Space accesses. |
0 | 0h | RW | IO Space Enable (IOSE) Controls a device's response to I/O Space accesses. A value of 0 disables the device response. A value of 1 allows the device to respond to I/O Space accesses. |