Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Device Capabilities (DEVCAP) – Offset 84
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:29 | 0h | RO | Reserved (RSVD1) This is a Reserved Register |
28 | 0h | RO | Reserved |
27:26 | 0h | RO | Captured Slot Power Limit Scale (SPLS) Hardwired to 0. |
25:18 | 0h | RO | Captured Slot Power Limit Value (SPLV) Hardwired to 0. |
17:16 | 0h | RO | Reserved (RSVD2) This is a Reserved Register |
15 | 0h | RO | Reserved |
14 | 0h | RO | Power Indicator Present (PIP) Hardwired to 0. |
13 | 0h | RO | Attention Indicator Present (AIP) Hardwired to 0. |
12 | 0h | RO | Attention Button Present (ABP) Hardwired to 0. |
11:9 | 0h | RO | Endpoint L1 Acceptable Latency (L1CAP) This bit field is defined in the PCI Express spec as RO. |
8:6 | 0h | RO | Endpoint L0s Acceptable Latency (L0SCAP) This bit field is defined in the PCI Express spec as RO. |
5 | 0h | RO | Extended Tag Field Support (ETCAP) Indicates 5 bit tag supported. |
4:3 | 0h | RO | Phantom Functions Supported (PFCAP) Indicates phantom functions not supported. |
2:0 | 0h | RO | Max Payload Size Supported (MPCAP) Indicates 128B maximum payload size capability. |