Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Capabilities List 2 & Message Control Register (CLIST2_MCTL) – Offset d0
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0h | RO | Reserved |
23 | 1h | RW/V | 64-bit Capable (64BC) Set to 1 to indicate that the GbE LAN Controller is capable of |
22:20 | 0h | RW/V | Multiple Message Enable (MME) Returns 000b to indicate that the GbE LAN controller only supports a single message. |
19:17 | 0h | RW/V | Multiple Message Capable (MMC) The GbE LAN controller does not support multiple |
16 | 0h | RW | Message Signal Interrupt Enable (MSIE) |
15:8 | e0h | RW/V | Next Capability (NEXT) Value of E0h points to the Function Level Reset capability structure.[BR] |
7:0 | 5h | RW/V | Capability ID (CID) Indicates the linked list item is a Message Signaled Interrupt Register. |