Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Global Bus Configuration 0 (GSBUSCFG0) – Offset c100
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:12 | 0h | RO | Reserved |
11 | 0h | RW | Data Access is Big-Endian (DATBIGEND) This bit controls the endian mode |
10:8 | 0h | RO | Reserved |
7 | 0h | RW | INCR256 Burst Type Enable (INCR256BRSTENA) If software set this bit to “1”, the master uses INCR to do the 256-beat burst. |
6 | 0h | RW | INCR128 Burst Type Enable (INCR128BRSTENA) If software set this bit to “1”, the master uses INCR to do the 128-beat burst. |
5 | 0h | RW | INCR64 Burst Type Enable (INCR64BRSTENA) If software set this bit to “1”, the master uses INCR to do the 64-beat burst. |
4 | 0h | RW | INCR32 Burst Type Enable (INCR32BRSTENA) If software set this bit to “1”, the master uses INCR to do the 32-beat burst. |
3 | 0h | RW | INCR16 Burst Type Enable (INCR16BRSTENA) If software set this bit to "1", the master uses INCR to do the 16-beat burst. |
2 | 1h | RW | INCR8 Burst Type Enable (INCR8BRSTENA) if software set this bit to "1", the master uses INCR to do the 8-beat burst |
1 | 1h | RW | INCR4 Burst Type Enable (INCR4BRSTENA) When this bit is enabled the controller is allowed to do bursts of beat length 1, 2, 3, and 4 |
0 | 0h | RW | Undefined Length INCR Burst Type Enable (INCRBRSTENA) When enabled, this has higher priority than other burst types. For the AHB |