Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Power Management Control And Status Register (PMECTRLSTATUS) – Offset 84
power management control and status register to set and read PME status PME enable No Soft reset and power state
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RO | Reserved Field (RESERVED0) This field is Reserved |
15 | 0h | RW/1C/P | Pme Status Field (PMESTATUS) This field is PME Status |
14:9 | 0h | RO | Reserved Field (RESERVED1) This field is Reserved |
8 | 0h | RW/P | Pme Enable Field (PMEENABLE) This field is PME Enable |
7:4 | 0h | RO | Reserved Field (RESERVED2) This field is Reserved |
3 | 1h | RO | No Soft Reset Field (NO_SOFT_RESET) This bit indicates that devices transitioning from D3hot to D0 because of Powerstate commands do not perform an internal reset |
2 | 0h | RO | Reserved Field (RESERVED3) This field is Reserved |
1:0 | 0h | RW | Power State Field (POWERSTATE) Power State: This field is used both to determine the current power state and to set a new power state |