Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
SMI Enable (GPI_SMI_EN_GPP_D_0) – Offset 294
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:5 | 0h | RO | Reserved |
4 | 0h | RW | GPI SMI Enable (GPI_SMI_EN_xxgpp_d_4) This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the corresponding GPIROUTSMI must be set to '1'. 0 = disable SMI generation 1 = enable SMI generation Bit assignment: Bit0 = Pad 0 Bit1 = Pad 1 Bit2 = Pad 2 ... Bit N-1 = Pad N-1 \t\t\t |
3 | 0h | RW | GPI SMI Enable (GPI_SMI_EN_xxgpp_d_3) This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the corresponding GPIROUTSMI must be set to '1'. 0 = disable SMI generation 1 = enable SMI generation Bit assignment: Bit0 = Pad 0 Bit1 = Pad 1 Bit2 = Pad 2 ... Bit N-1 = Pad N-1 \t\t\t |
2 | 0h | RW | GPI SMI Enable (GPI_SMI_EN_xxgpp_d_2) Same description as bit 0. |
1 | 0h | RW | GPI SMI Enable (GPI_SMI_EN_xxgpp_d_1) Same description as bit 0. |
0 | 0h | RW | GPI SMI Enable (GPI_SMI_EN_xxgpp_d_0) This bit is used to enable/disable the generation of SMI when the corresponding GPI_SMI_STS bit is set. The pad must also be routed for SMI functionality in order for SMI to be generated, i.e. the corresponding GPIROUTSMI must be set to '1'. |