Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
EC Thermal Sensor Reporting Enable (ECRPTEN) – Offset 1510
This is a BIOS programmable register used to enable reporting of temperature by PMC to EC over eSPI. Setting bit 0 will cause a GCR interrupt to PMC FW through generic GCR mechanism. FW needs to enable the periodic reporting task accordingly. Bit 31 is uses as a lock bit to prevent any further writes to bit 0.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RW/L | Lock-Down Bit (ECRPTENLOCK) When written to 1, this bit prevents any more writes to this register. |
30:1 | 0h | RO | Reserved |
0 | 0h | RW/L | Enable PMC to EC Temperature Reporting (EN_PMC_TO_EC_TEMP_RPT) 0x1 : Enables the reporting of the SOC tile temperature to the EC (via SMBUS or eSPI). Note that this must also be set if ME needs access to the SOC tile temperature. Once enabled this bit should not be cleared by SW. If it is cleared then the EC may get an undefined value. SW has no need to dynamically disable and then re-enable this bit. |