Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Pad Configuration Lock GPIO TxState Register (PADCFGLOCKTX_GPP_C_0) – Offset 124
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0h | RO | Reserved (RSVD_0)
|
23 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_23) Same description as bit 0 |
22 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_22) Same description as bit 0 |
21 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_21) Same description as bit 0 |
20 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_20) Same description as bit 0 |
19 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_19) Same description as bit 0 |
18 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_18) Same description as bit 0 |
17 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_17) Same description as bit 0 |
16 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_16) Same description as bit 0 |
15 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_15) Same description as bit 0 |
14 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_14) Same description as bit 0 |
13 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_13) Same description as bit 0 |
12 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_12) Same description as bit 0 |
11 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_11) Same description as bit 0 |
10 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_10) Same description as bit 0 |
9 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_9) Same description as bit 0 |
8 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_8) Same description as bit 0 |
7 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_7) Same description as bit 0 |
6 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_6) Same description as bit 0 |
5 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_5) Same description as bit 0 |
4 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_4) Same description as bit 0 |
3 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_3) Same description as bit 0 |
2 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_2) Same description as bit 0 |
1 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_1) Same description as bit 0 |
0 | 0h | RW | Pad Config Lock TXState (PADCFGLOCKTX_xxgpp_c_0) PadCfgLockTx locks the GPIOTxState bit from being configured. The GPIOTxState register becomes Read-Only and software writes to the register have no effect. |