Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Command Register (CMD) – Offset 4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:11 | 0h | RO | Reserved (RSVD0)
|
10 | 0h | RW | Interrupt Disable (ID) Enables the device to assert an INTx#. When set, the Intel HD Audio subsystems INTx# signal will be de-asserted. When cleared, the INTx# signal may be asserted. Note that this bit does not affect the generation of MSIs. |
9 | 0h | RO | Fast Back to Back Enable (FBE) Not implemented. Hardwired to 0. |
8 | 0h | RW | SERR Enable (SEN) As a PCI device, this bit is an enable bit for the SERR# driver.As a PCIe device, this bit enables (when set) reporting of Non-fatal and Fatal errors detected by the Function to the Root Complex. |
7 | 0h | RO | Wait Cycle Control (WCC) Not implemented. Hardwired to 0. |
6 | 0h | RW | Parity Error Response (PER) As a PCI device, this bit controls the devices response to parity errors. As a PCIe device, this bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. |
5 | 0h | RO | VGA Palette Snoop (VPS) Not implemented. Hardwired to 0. |
4 | 0h | RO | Memory Write and Invalidate Enable (MWI) Not implemented. Hardwired to 0. |
3 | 0h | RO | Special Cycle Enable (SCE) Not implemented. Hardwired to 0. |
2 | 0h | RW | Bus Master Enable (BME) Controls standard PCI bus mastering capabilities for Memory and IO, reads and writes. Note that this also controls MSI generation since MSI are essentially Memory writes. |
1 | 0h | RW | Memory Space Enable (MSE) When set, enables memory space accesses to the Intel HD Audio subsystem. |
0 | 0h | RO | I/O Space (IOS) The ACE IP does not implement IO Space, therefore this bit is hardwired to 0. |