Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Touch Host Controller Control Register (THC_M_PRT_CONTROL) – Offset 1008
THC Control Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:30 | 0h | RO | Port type for this port instance (PORT_TYPE) 00: SPI port |
29 | 0h | RO/V | Indication of SPI IO (SPI_IO_RDY) 0: This SPI port IO is not ready for operation |
28 | 1h | RW/L | Whether this port is supported or not (PORT_SUPPORTED) 0: This port is not supported |
27 | 0h | RW/L | Lock bit for several BIOS registers (THC_BIOS_LOCK_EN) 0: The registers listed below are not locked |
26 | 0h | RO | Reserved (RSVD_26) Reserved. |
25:24 | 0h | RW | Arbitration policy register of THC (THC_ARB_POLICY) This policy decides the granuarity of the PIO, TXDMA and RXDMA arbiter. |
23 | 0h | RO | Reserved (RSVD_23) Reserved. |
22:20 | 0h | RO | Port index under this THC (PORT_INDEX) This field indicates the 0-based port index of this port in the THC. |
19 | 0h | RO | Reserved (RSVD_19) Reserved. |
18:16 | 0h | RO | THC Instance index of this THC (THC_INSTANCE_INDEX) This field indicates the 0-based instance index of this THC. |
15:14 | 0h | RO | Reserved (RSVD_15_14) Reserved. |
13 | 0h | RW/L | THC Locking bit to lock driver registers (THC_DRV_LOCK_EN) When set to 1 , prevents INT_SW_DMA_EN, INT_SW_DMA_EN2 from being changed. This bit can only be written from 0 to 1 once. Once set to 1, this bit can only be cleared by a hardware reset. |
12:5 | 0h | RO | Reserved (RSVD_12_5) Reserved. |
4 | 0h | RW | SW GPIO Interrupt Reset (SWGPIO_INT) 1: Assert SW GPIO interrupt through vGPIO. |
3 | 0h | RW | Device GPIO Reset (DEVRST) 1: Deassert Device reset/power on through GPIO. |
2 | 1h | RO/V | Hardware Status for Quiesce Status bit (THC_DEVINT_QUIESCE_HW_STS) HW will set this bit once RX sequencer is IDLE, after completing processing of any microframe that started before the THC_DEVINT_QUIESCE_EN. SW cannot clear THC_DEVINT_QUIESCE_EN until it sees this bit set |
1 | 1h | RW | Quiesce bit for the device interrupt (THC_DEVINT_QUIESCE_EN) When this bit is set, THC shall complete servicing the current touch microframe or current device interrupt, and ignore the TIC's interrupt (including touch and non-touch interrupt) until the bit is cleared by SW. When SW writes 1 to this bit, THC is expected to complete processing the current microframe and then set THC_DEVINT_QUIESCE_HW_STS. THC shall not drop any outstanding interrupt asserted when THC_DEVINT_QUIESCE_EN is set. |
0 | 0h | RO | Reserved |