Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
SBI Status (SBISTAT) – Offset d8
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:8 | 0h | RW | Opcode (OPCODE) This is the Opcode sent in the IOSF sideband message. |
7 | 0h | RW | Posted (POSTED) When set to 1, the message will be send as a posted message instead of non-posted. This should only be used if the receiver is known to support posted operations for the specified operation. |
6:3 | 0h | RO | Reserved |
2:1 | 0h | RW/V | Response Status (RESPONSE) 00 - Successful |
0 | 0h | RW/1S | Initiate/ Ready# (INITRDY) 0: The IOSF sideband interface is ready for a new transaction |