Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Processing Pipe Control (PPCTL) – Offset 804
This register controls the processing pipe operation.Note: The PROCEN bits should only be modified when the corresponding host DMA and link DMA are idle, i.e. RUN bits are cleared, and DMA contexts have been destroyed through SRST bits if it was previously activated.Note: The GPROCEN bit does not really enable or disable the DSP offload operation, but mainly to support some legacy Intel HD Audio driver software such that if GPROCEN = 0, DSPxBA (BAR2) is mapped to the Intel HD Audio memory mapped configuration registers, for compliancy with some legacy SW implementation. If GPROCEN = 1, only then DSPxBA (BAR2) is mapped to the actual DSP memory mapped configuration registers.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31 | 0h | RW | Processing Interrupt Enable (PIE) Enables the general interrupt for the DSP subsystem. When set to 1 (and GIE is enabled), the DSP subsystem generates an interrupt when the PIS bit gets set. |
30 | 0h | RW | Global Processing Enable (GPROCEN) When set to 1, it indicates that the DSP subsystem is enabled for operation. |
29:19 | 0h | RO | Reserved (RSVD0) This is a Reserved Register |
18:0 | 0h | RW/L | Processing Enable (PROCEN) When set to 1 the DMA engine associated with this stream will be enabled to route the audio stream to DSP audio pipes in the DSP subsystem for processing.When cleared to 0 the DMA engine associated with this stream will be bypassing the DSP subsystem and route the audio stream directly to the audio link.Locked to appear as RO per allocation programmed in HfHDASDA.OSC + HfHDASDA.ISC register fields. |