Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Device Idle Pointer Register (HECI1_DEVIDLEPTR) – Offset b0
Device Idle Pointer Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:4 | 800h | RO | Device Idle MMIO Offset Location (DEVIDLELOC) This register contains the location pointer to the DevIdle register in MMIO space, as an offset |
3:1 | 0h | RO | Base Address Register Number (BARNUM) Contains the 0's based AR Number of the BAR which contains the location of the SW LTR MMIO |
0 | 1h | RO | Valid (Valid) Set to 1'b1 to indicate that the function has implemented a SW LTR register as specified DevIdle |