Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
SoC Internal Fabric Thermal Throttling Configuration (SOCIFTTC) – Offset 15a8
Configuration data for SoC internal fabric thermal throttling. Software is required to make changes to the Fabric Throttle Period and Fabric Throttle Period Enable bits only while the SoC Internal Fabric Thermal Throttling Mechanism is disabled (i.e., bit 0 is clear).
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:16 | 0h | RO | Reserved (RSVD1) Reserved |
15 | 1h | RW/L | Level 3 Fabric Throttle Period Enable (L3FTPE) 0: Level 3 Fabric Throttle Period will not be used. Fabric Throttling is treated as disabled during Throttle Level 3 |
14 | 1h | RW/L | Level 2 Fabric Throttle Period Enable (L2FTPE) 0: Level 2 Fabric Throttle Period will not be used. Fabric Throttling is treated as disabled during Throttle Level 2 |
13 | 1h | RW/L | Level 1 Fabric Throttle Period Enable (L1FTPE) 0: Level 1 Fabric Throttle Period will not be used. Fabric Throttling is treated as disabled during Throttle Level 1 |
12 | 1h | RW/L | Level 0 Fabric Throttle Period Enable (L0FTPE) 0: Level 0 Fabric Throttle Period will not be used. Fabric Throttling is treated as disabled during Throttle Level 0 |
11:10 | 0h | RW/L | Level 3 Fabric Throttle Period (L3FTP) If the SoC Internal Fabric Thermal Throttling Mechanism Enable is set and the Level 3 Fabric Throttle Period Enable is set, then this register determines the period of arb_stall when the Thermal Sensor indicates that Level 3 Throttling |
9:8 | 0h | RW/L | Level 2 Fabric Throttle Period (L2FTP) If the SoC Internal Fabric Thermal Throttling Mechanism Enable is set and the Level 2 Fabric Throttle Period Enable is set, then this register determines the period of arb_stall when the Thermal Sensor indicates that Level 2 Throttling |
7:6 | 0h | RW/L | Level 1 Fabric Throttle Period (L1FTP) If the SoC Internal Fabric Thermal Throttling Mechanism Enable is set and the Level 1 Fabric Throttle Period Enable is set, then this register determines the period of arb_stall when the Thermal Sensor indicates that Level 1 Throttling |
5:4 | 0h | RW/L | Level 0 Fabric Throttle Period (L0FTP) If the SoC Internal Fabric Thermal Throttling Mechanism Enable is set and the Level 0 Fabric Throttle Period Enable is set, then this register determines the period of arb_stall when the Thermal Sensor indicates that Level 0 Throttling |
3:2 | 0h | RO | Reserved (RSVD) Reserved |
1 | 0h | RW/L | SoC Internal Fabric Thermal Throttling Mechanism Lock (SOCIFTTML) When this bit is set, writes to bits 31:2 of this register will have no effect. Once this bit is set, writes of 0 to this bit will have no effect (i.e. once set, this bit can only be cleared by host reset). |
0 | 0h | RW | SoC Internal Fabric Thermal Throttling Mechanism Enable (SOCIFTTME) SoC Internal Fabric Thermal Throttling Mechanism Enable. |