Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
NMI Status (GPI_NMI_STS_GPP_D_0) – Offset 2b4
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:5 | 0h | RO | Reserved |
4 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_d_4) Same description as bit 0. |
3 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_d_3) Same description as bit 0. |
2 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_d_2) Same description as bit 0. |
1 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_d_1) Same description as bit 0. |
0 | 0h | RW/1C | GPI NMI Status (GPI_NMI_STS_xxgpp_d_0) This bit is set to '1' by hardware when an edge event is detected (See RxEdCfg, RxInv) on pad and all the following conditions are true: |