Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Shared SRAM PCI Configuration (D20:F2) Registers
The following registers are at Device 20:Function 2.
Offset | Size (Bytes) | Register Name (Register Symbol) | Scope | Default Value |
---|---|---|---|---|
0h | 4 | Package | XXXX8086h | |
4h | 4 | Package | 00100000h | |
8h | 4 | Package | 050000XXh | |
ch | 4 | CLLATHEADERBIST Cache Line Latency Header And BIST (CLLATHEADERBIST) | Package | 00000000h |
10h | 4 | Package | 00000004h | |
14h | 4 | Package | 00000000h | |
18h | 4 | Package | 00000004h | |
1ch | 4 | Package | 00000000h | |
2ch | 4 | Package | 00000000h | |
30h | 4 | Package | 00000000h | |
34h | 4 | Package | 00000080h | |
3ch | 4 | Package | 00000000h | |
80h | 4 | Package | 00030001h | |
84h | 4 | Package | 00000008h | |
90h | 4 | Package | 00000000h | |
94h | 4 | Package | 00000000h | |
98h | 4 | D0I3 CONTROL SW LTR MMIO REG (D0I3_CONTROL_SW_LTR_MMIO_REG) | Package | 00000000h |
9ch | 4 | Package | 00000000h | |
a0h | 4 | D0I3 MAX POW LAT PG CONFIG (D0I3_MAX_POW_LAT_PG_CONFIG) | Package | 00000000h |
b0h | 4 | Package | 00000000h | |
b4h | 4 | Package | 00000000h | |
b8h | 4 | Package | 00000000h | |
bch | 4 | Package | 00000000h | |
c0h | 4 | Package | 00000000h |