Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Power and Reset Status (PRSTS) – Offset 1810
Bits in this register only need to be valid for reading when the Main power well is up. However, since some of the events may initially be detected while the Main power well is down, they are marked as suspend well bits. All suspend well bits in this register are reset by global_rst_b.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:6 | 0h | RO | Reserved |
5 | 0h | RW/1C/V | Wake On LAN Override Wake Status (WOL_OVR_WK_STS) This bit gets set when integrated LAN Signals a Power Management Event AND the system is in S5. BIOS can read this status bit to determine this wake source. Software clears this bit by writing a 1 to it. |
4:1 | 0h | RO | Reserved |
0 | 0h | RW/1C/V | ME_HOST_WAKE_STS (ME_HOST_WAKE_STS) This bit is set when the Intel CSME generates a non-maskable wake event and is not affected by any other enable bit. When this bit is set, the host power management logic wakes to S0. |