Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_D_0) – Offset 254
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0h | RO | Reserved |
23 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_23) Same description as bit 0 |
22 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_22) Same description as bit 0 |
21 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_21) Same description as bit 0 |
20 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_20) Same description as bit 0 |
19 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_19) Same description as bit 0 |
18 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_18) Same description as bit 0 |
17 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_17) Same description as bit 0 |
16 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_16) Same description as bit 0 |
15 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_15) Same description as bit 0 |
14 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_14) Same description as bit 0 |
13 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_13) Same description as bit 0 |
12 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_12) Same description as bit 0 |
11 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_11) Same description as bit 0 |
10 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_10) Same description as bit 0 |
9 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_9) Same description as bit 0 |
8 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_8) Same description as bit 0 |
7 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_7) Same description as bit 0 |
6 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_6) Same description as bit 0 |
5 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_5) Same description as bit 0 |
4 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_4) Same description as bit 0 |
3 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_3) Same description as bit 0 |
2 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_2) Same description as bit 0 |
1 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_1) Same description as bit 0 |
0 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_d_0) This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the corresponding GPI_GPE_STS[i] bit is set. |