Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Status Register (STS) – Offset 6
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15 | 0h | RW/1C/V | Detected Parity Error (DPE) As a PCI device, this bit is always 0. As a PCIe device, this bit is set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command register. |
14 | 0h | RW/1C/V | SERR# Status (SERRS) As a PCI device, this bit is set when SERR# is signaled. As a PCIe device, this bit is Set when a Function sends an ERR_FATAL or ERR_NONFATAL Message, and the SERR# Enable bit in the Command register is 1. |
13 | 0h | RW/1C/V | Received Master Abort (RMA) If the completion status received from IOSF is UR, this bit is set. SW writes a 1 to this bit to clear it. |
12 | 0h | RW/1C/V | Received Target Abort (RTA) If the completion status received from IOSF is CA, this bit is set. SW writes a 1 to this bit to clear it. |
11 | 0h | RO | Signaled Target-Abort (STA) Not implemented. Hardwired to 0. |
10:9 | 0h | RO | DEVSEL# Timing Status (DEVT) Does not apply. Hardwired to 0. |
8 | 0h | RW/1C/V | Master Data Parity Error (MDPE) As a PCI device, this bit is always 0. As a PCIe device, this bit is Set by an Endpoint Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: Endpoint receives a Poisoned Completion Endpoint or transmits a Poisoned Request |
7 | 0h | RO | Fast Back to Back Capable (FBC) Does not apply. Hardwired to 0. |
6 | 0h | RO | Reserved (RSVD1) Reserved |
5 | 0h | RO | 66 MHz Capable (C66) Does not apply. Hardwired to 0. |
4 | 1h | RO | Capabilities List Exists (CLIST) Indicates that the controller contains a capabilities pointer list. The first item is pointed to by looking at configuration offset 34h. |
3 | 0h | RO/V | Interrupt Status (IS) Reflects the state of the INTx# signal at the input of the enable/disable circuit. |
2:1 | 0h | RO | Reserved (RSVD2) This is a Reserved Register |
0 | 0h | RO | Immediate Readiness (IMRD) Not implemented. Hardwired to 0. |