Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG RawErr (RawErr) – Offset ae0
RawErr - Raw Status for Error Interrupts Register
Error interrupt will be asserted by the DMA in the following cases:
IOSF Fabric returns an Unsuccessful Completion with UR Completion Status for a Non-Posted trasnsaction
issued by the DMA to Memory. This error occurs when an invalid address range is programed into the DMA
SRC/Dest Field outside of the Host memory region on the memory side of the DMA transaction IOSF2OCP bridge will return error (triggering error interrupt from DMA) if the IOSF2OCP Bridge is
programmed incorrectly.
Peripheral side trasactions where invalid addressing can result in an OCP fabric error which will be translated
into an Error Interupt.
The SW should view this error as a serious programming error and handle it according to the specified error handling
procedures for the product and OS.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:2 | 0h | NA | RSVD (RSVD) Reserved |
1:0 | 0h | RO | RAW (RAW) Raw interrupt status for ch 1 and ch0 |