Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Version Register (VS) – Offset 1
Each I/O APIC contains a hardwired Version Register that identifies different implementation of APIC and their versions. The maximum redirection entry information is also in this register to let software know how many interrupt are supported by this APIC.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0h | RO | Reserved (RSVD) Reserved |
23:16 | 77h | RW/O | Maximum Redirection Entries (MRE) This is the entry number (0 being the lowest entry) of the highest entry in the redirection table. It is equal to the number of interrupt input pins minus one and is in the range of 0 through 239. This field is defaulted to 17h to indicate 24 interrupts. |
15 | 0h | RO | Pin Assertion Register Supported (PRQ) Indicate that the IOxAPIC does not implement the Pin Assertion Register. |
14:8 | 0h | RO | Reserved (RSVD_1) Reserved |
7:0 | 20h | RO | Version field (VS) Identifies the implementation version as IOxAPIC. |