Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
REG CTL_LO1 (CTL_LO1) – Offset 870
This register contains fields that control the DMA transfer.The CTL_LO register is part of the block descriptor (linked
list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when
block chaining is enabled.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:29 | 0h | NA | RSVD (RSVD) Reserved |
28 | 0h | RW | LLP_SRC_EN (LLP_SRC_EN) Block chaining is enabled on the source side only if the LLP_SRC_EN field is high |
27 | 0h | RW | LLP_DST_EN (LLP_DST_EN) Block chaining is enabled on the destination side only if the LLP_DST_EN field is |
26:22 | 0h | NA | RSVD1 (RSVD1) Reserved |
21:20 | 0h | RW | TT_FC (TT_FC) Transfer Type and Flow Control. The following transfer types are supported. |
19 | 0h | NA | RSVD2 (RSVD2) Reserved |
18 | 0h | RW | DST_SCATTER_EN (DST_SCATTER_EN) Destination scatter enable bit: |
17 | 0h | RW | SRC_GATHER_EN (SRC_GATHER_EN) Source gather enable bit: |
16:14 | 0h | RW | SRC_MSIZE (SRC_MSIZE) Source Burst Transaction Length. Number of data items, each of width |
13:11 | 0h | RW | DEST_MSIZE (DEST_MSIZE) Destination Burst Transaction Length. Number of data items, each of width |
10 | 0h | RW | SINC (SINC) Source Address Increment. Indicates whether to increment or decrement the source address on every source |
9 | 0h | NA | RSVD3 (RSVD3) Reserved |
8 | 0h | RW | DINC (DINC) Destination Address Increment. |
7 | 0h | NA | RSVD4 (RSVD4) Reserved |
6:4 | 0h | RW | SRC_TR_WIDTH (SRC_TR_WIDTH) Source Transfer Width. |
3:1 | 0h | RW | DST_TR_WIDTH (DST_TR_WIDTH) BURST SIZE (in DW) = (2^ MSIZE) (i.e. 2 to-the-power-of MSIZE) |
0 | 0h | RW | INT_EN (INT_EN) Interrupt Enable Bit. If set, then all interrupt-generating sources are enabled. |