Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
GPI General Purpose Events Enable (GPI_GPE_EN_GPP_S_0) – Offset 250
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:8 | 0h | RO | Reserved (RSVD_0)
|
7 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_s_7) Same description as bit 0 |
6 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_s_6) Same description as bit 0 |
5 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_s_5) Same description as bit 0 |
4 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_s_4) Same description as bit 0 |
3 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_s_3) Same description as bit 0 |
2 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_s_2) Same description as bit 0 |
1 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_s_1) Same description as bit 0 |
0 | 0h | RW | GPI General Purpose Events Enable (GPI_GPE_EN_xxgpp_s_0) This bit is used to enable/disable the generation of GPE to cause SCI and/or wake when the corresponding GPI_GPE_STS bit is set. |