Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
BIOS Control (ESPI_BC) – Offset dc
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:12 | 0h | RO | Reserved |
11 | 0h | RW/L | BIOS Write Reporting (Async-SMI) Enable (BWRE) 1'b0: Disable reporting of BIOS Write event. |
10 | 0h | RW/1C/V | BIOS Write Status (BWRS) HW sets this bit if a memory write access is detected to a protected BIOS range. |
9 | 0h | RO | Reserved |
8 | 0h | RW/1C/V | BIOS Write Protect Disable Status (BWPDS) HW sets this bit if configuration write access is detected to protected WPD bit. |
7 | 0h | RW/L | BIOS Interface Lock-Down (BILD) When set, prevents BC.TS and BC.BBS from being changed. This bit can only be written from 0 to 1 once. |
6 | 0h | RW/V/L | Boot BIOS Strap (BBS) This field determines the destination of accesses to the BIOS memory range. |
5 | 1h | RW/L | Enable InSMM.STS (EISS) When this bit is set, the BIOS region is not writable until SMM sets the InSMM.STS bit. BIOS Flash is writable if WPD is a 1. If this bit (5) is set, then WPD must be a 1 and InSMM.STS (0xFED3_0880(0)) must be 1 also. |
4 | 0h | RO/V | Top Swap (TS) When set, the processor will invert either A16, A17, or A18 for cycles going to the BIOS space (but not the Feature space). When cleared, the processor will not invert A16. |
3 | 0h | RO | Reserved |
2 | 0h | RO/V | eSPI Enable Pin Strap (ESPI) eSPI Enable Pin Strap (ESPI): This field determines the destination of accesses to the D31:F0 and related Fixed and Variable IO and Memory decode ranges, including BIOS memory range. |
1 | 0h | RW/L | Lock Enable (LE) When set, setting the WP bit will cause SMI. |
0 | 0h | RW | Write Protect Disable (WPD) When set, access to the BIOS space is enabled for both read and write cycles to BIOS. When cleared, only read cycles are permitted to the SPI flash. When this bit is written from a 0 to a 1 and the LE bit is also set, an SMI# is generated. This ensures that only SMM code can update BIOS. |