Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Power Management Capabilities (CNVI_WIFI_PMC) – Offset c8
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:27 | 19h | RO | PME Support (PME_SUPRT) PME Support, indicates the power states in which the device may assert PME. |
26 | 0h | RO | D2 Power Management (D2_PWR_MANG) D2 Power Management State support. |
25 | 0h | RO | D1 Power Management (D1_PWR_MANG) D1 Power Management State support |
24:22 | 0h | RO | Auxiliary Current (AUX_CUR) AUX Current (Used data register instead) |
21 | 1h | RO | Device Space Interrupt (DEV_SPC_INT) Device Specific Initialization |
20 | 0h | RO | Reserved |
19 | 0h | RO | PME Clock (PME_CLK) PME Clock, does not apply to PCI Express - Hardwired. |
18:16 | 3h | RO | Version (VERSION) value indicates that this function complies with the Revision 1.2. |
15:8 | d0h | RO | Power Management Next Pointer (PMC_NXT_PTR) Next PTR, pointing to the location of next item in the functions capability list. Hardwired. |
7:0 | 1h | RO | Power Management Capability (PMC_CAP_ID) Capability ID, Indicates the linked list item is the PCI Power Management Registers. Hardwired. |