Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
GPI Interrupt Status (GPI_IS_GPP_H_0) – Offset 200
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:26 | 0h | RO | Reserved (RSVD_0)
|
25:23 | 0h | RO | Reserved |
22 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_22) Same description as bit 0. |
21 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_21) Same description as bit 0. |
20 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_20) Same description as bit 0. |
19 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_19) Same description as bit 0. |
18 | 0h | RO | Reserved |
17 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_17) Same description as bit 0. |
16 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_16) Same description as bit 0. |
15 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_15) Same description as bit 0. |
14 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_14) Same description as bit 0. |
13 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_13) Same description as bit 0. |
12 | 0h | RO | Reserved |
11 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_11) Same description as bit 0. |
10 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_10) Same description as bit 0. |
9 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_9) Same description as bit 0. |
8 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_8) Same description as bit 0. |
7 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_7) Same description as bit 0. |
6 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_6) Same description as bit 0. |
5 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_5) Same description as bit 0. |
4 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_4) Same description as bit 0. |
3 | 0h | RO | Reserved |
2 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_2) Same description as bit 0. |
1 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_1) Same description as bit 0. |
0 | 0h | RW/1C | GPI Interrupt Status (GPI_INT_STS_xxgpp_h_0) This bit is set to '1' by hardware when either an edge or a level event is detected (See RxEdCfg RxInv) on pad and all the following conditions are true: |