Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
TCO2_STS Register (TSTS2) – Offset 6
TCO2_STS Register
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15:5 | 0h | RO | Reserved |
4 | 0h | RW/1C | SMLINK_SLAVE_SMI_STS (SMLINK_SLAVE_SMI_STS) This bit is set to 1 when it receives the SMI message (encoding 08h in the command type) on the SMLinks Slave Interface. Software clears the bit by writing a 1 to this bit position. It is reset by RSMRST#, but not by the PCI Reset associated with exit from S3-S5 states. This allows the software (presumably BIOS) to get the interrupt, see this new bit set, and decidedly go into the pre-determined (by local policy) sleep state. The advantage here is that race conditions are eliminated if the bit is only meant for power-down instead of potentially being meant for power-up or power-down depending on the current state (like the real power button). |
3 | 0h | RO | Reserved |
2 | 0h | RO/V | NO_REBOOT_PIN_STRAP_STATUS (NRSTRAP_STS) This bit reflects the state of the No_Reboot strap that is sampled on PWROK rise. |
1 | 0h | RW/1C | SECOND_TO_STS (SECOND_TO_STS) This bit is set to 1 to indicate that the TIMEOUT bit had been (or is currently) set and a second timeout occurred before the TCO_RLD register was written. If this bit is set and the NO_REBOOT config bit is 0, the sytem will reboot after the second timeout. The reboot is done by asserting PLTRST#. This bit is only cleared by writing a 1 to this bit or by a RSMRST#. |
0 | 0h | RW/1C | INTRD_DET (INTRD_DET) Intruder Detect. Bit set to 1 to indicate that an intrusion was detected. This is latched. This bit is cleared by writing a 1 to this bit or by RTCRST# assertion. This bit is backed in the RTC Well. |