Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Pad Ownership (PAD_OWN_GPP_H_0) – Offset b0
Note: bits corresponding to unavailable GPP_H pins are reserved.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:30 | 0h | RO | Reserved |
29:28 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_h_7) Same description as bits[1:0]. |
27:26 | 0h | RO | Reserved |
25:24 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_h_6) Same description as bits[1:0]. |
23:22 | 0h | RO | Reserved |
21:20 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_h_5) Same description as bits[1:0]. |
19:18 | 0h | RO | Reserved |
17:16 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_h_4) Same description as bits[1:0]. |
15:14 | 0h | RO | Reserved |
13:12 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_h_3) Same description as bits[1:0]. |
11:10 | 0h | RO | Reserved |
9:8 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_h_2) Same description as bits[1:0]. |
7:6 | 0h | RO | Reserved |
5:4 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_h_1) Same description as bits[1:0]. |
3:2 | 0h | RO | Reserved (RSVD_7)
|
1:0 | 0h | RW | Pad Ownership (PAD_OWN_xxgpp_h_0) 00 = Host GPIO ACPI Mode or GPIO Driver Mode. Host software (ACPI or GPIO Driver) has ownership of the pad. In Host GPIO Driver Mode (refer to HOSTSW_OWN), GPIO input event update is limited to GPI_STS update only. |