Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Capabilities List and Power Managment Capabilities Register (CLIST1_PMC) – Offset c8
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:27 | 0h | RW/V | PME_SUPPORT (PMES) This five-bit field indicates the power states in which the function may |
26 | 0h | RW/V | D2_SUPPORT (D2S) The D2 state is not supported. |
25 | 0h | RW/V | D1_SUPPORT (D1S) The D1 state is not supported. |
24:22 | 0h | RW/V | AUX_CURRENT (AC) Required current defined in the Data register. |
21 | 1h | RW/V | Device Specific Initialization (DSI) Set to 1. The GbE LAN Controller requires its device |
20 | 0h | RO | Reserved |
19 | 0h | RW/V | PME Clock (PMEC) Hardwired to 0. |
18:16 | 3h | RW/V | Version (VER) Hardwired to 010b to indicate support for Revision 1.1 of the PCI Power Management Specification. |
15:8 | d0h | RW/V | Next Capability (NEXT) Value of D0h indicates the location of the next pointer. |
7:0 | 1h | RW/V | Capability ID (CID) Indicates the linked list item is a PCI Power Management Register. |