Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Message Signaled Interrupt Message Upper Address (MUA) – Offset 88
This is the Message Signaled Interrupt Message Upper Address registers. Refer description for each individual field below for more details of the register functionality.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:0 | 0h | RW | Upper Address (UADDR) System-specified message upper address. |