Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
PGD PG_ACK Status Register 1 (PPASR1) – Offset 1d84
PGD PG ACK Status Register 1
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:29 | 0h | RO | Reserved |
28 | 0h | RO/V | HDA Power Gate Power Gate ACK Status (AGT60_PG_ACK_STS) Same description as bit 0. |
27 | 0h | RO/V | HDA Power Gate Power Gate ACK Status (AGT59_PG_ACK_STS) Same description as bit 0. |
26 | 0h | RO/V | HDA Power Gate Power Gate ACK Status (AGT58_PG_ACK_STS) Same description as bit 0. |
25 | 0h | RO/V | Intel Trace Hub Power Gate ACK Status (AGT57_PG_ACK_STS) Same description as bit 0. |
24:23 | 0h | RO | Reserved |
22 | 0h | RO/V | PCIe Controller F Power Gate ACK Status (AGT54_PG_ACK_STS) Same description as bit 0. |
21 | 0h | RO | Reserved |
20 | 0h | RO/V | UFS Power Gate ACK Status (AGT52_PG_ACK_STS) Same description as bit 0. |
19 | 0h | RO/V | CNVi-WIFI Power Gate ACK Status (AGT51_PG_ACK_STS) Same description as bit 0. |
18:2 | 0h | RO | Reserved |
1 | 0h | RO/V | CSME SRAM Power Gate Ack Status (AGT33_PG_ACK_STS) Same description as bit 0. |
0 | 0h | RO/V | CSME-USBr Power Gate ACK Status (AGT32_PG_ACK_STS) This indicates the current status of the controller. |