Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Register B General Configuration (Register_B) – Offset b
RTC Index: 0Bh
Attribute: Read/Write
Default Value: 10000UUU
Size: 8-bit
Lockable: No
Power Well: RTC
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
7 | 1h | RW | Update Cycle Inhibit (RTC_SET) Enables/Inhibits the update cycles. When SET is 0, update cycle occurs normally once each second. If set to one, a current update cycle will abort and subsequent update cycles will not occur until SET is returned to zero. |
6 | 0h | RW | Periodic Interrupt Enable (PIE) If set to 1, the Periodic Interrupt Enable (PIE) bit allows an interrupt to occur with a time base set with the RS bits of register A. This bit is cleared by RSMRST#, but not on any other reset |
5 | 0h | RW | Alarm Interrupt Enable (AIE) If set to one, the Alarm Interrupt Enable (AIE) bit allows an interrupt to occur when the AF is one as set from an alarm match from the update cycle. An alarm can occur once a second, one an hour, once a day, or once a month. This bit is cleared by RTCRST#, but not on any other reset |
4 | 0h | RW | Update-ended Interrupt Enable: (UIE) If set to one, the Update-ended Interrupt Enable (UIE) bit allows an interrupt to occur when the update cycle ends. This bit is cleared by RSMRST#, but not on any other reset |
3 | 0h | RW | Square Wave Enable (SQWE) The Square Wave Enable bit serves no function in this device, yet is left in this register bank to provide compatibility with the Motorola 146818B. There is not SQW pin on this device. This bit is cleared by RSMRST#, but not on any other reset. |
2 | 0h | RW | Data Mode (DM) The Data Mode (DM) bit specifies either binary or BCD data representation. A one denotes binary, and zero denotes BCD. This bit is not affected by RSMRST# nor any other reset signal. |
1 | 0h | RW | Hour Format (HOURFORM) This bit indicates the hour byte format. If one, twenty-four hour mode is selected. If zero, twelve-hour mode is selected. In twelve hour mode, the seventh bit represents AM as zero and PM as one. This bit is not affected by RSMRST# nor any other reset signal. |
0 | 0h | RW | Daylight Savings Enable (DSE) Reserved |