Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Device Control Register (DEVCTL) – Offset 88
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
15 | 0h | RO | RESERVED (RSVD) RESERVED |
14:12 | 0h | RO | Max_Read_Request_Size (MRRS) This field sets the maximum Read Request size for the Function as a Requester. The Function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: |
11 | 0h | RO | Enable No Snoop (ENS) If this bit is Set, the Function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency. This bit is permitted to be hardwired to 0b if a Function would never Set the No Snoop attribute in transactions it initiates |
10 | 0h | RO | Aux Power PM Enable (APPE) When Set this bit, enables a Function to draw Aux power independent of PME Aux power. Functions that do not implement this capability hardwire this bit to 0b. |
9 | 0h | RO | Phantom Functions Enable (PFE) When Set, this bit enables a Function to use unclaimed Functions as Phantom Functions to extend the number of outstanding transaction identifiers. Functions that do not implement this capability hardwire this bit to 0b. |
8 | 0h | RO | Extended Tag Field Enable (ETFE) When Set, this bit enables a Function to use an 8-bit Tag field as a Requester. If the bit is Clear, the Function is restricted to a 5-bit Tag field. Functions that do not implement this capability hardwire this bit to 0b. |
7:5 | 2h | RW | Max_Payload_Size (MPS) (MPS) This field sets maximum TLP payload size for the Function. As a Receiver, the Function must handle TLPs as large as the set value. As a Transmitter, the Function must not generate TLPs exceeding the set value. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field in the Device Capabilities register. |
4 | 0h | RO | Enable Relaxed Ordering (ERO) If this bit is Set, the Function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering. A Function is permitted to hardwire this bit to 0b if it never sets the Relaxed Ordering attribute in transactions it initiates as a Requester |
3 | 0h | RW | Unsupported Request Reporting Enable (URRE) This bit, in conjunction with other bits, controls the signaling of Unsupported Request Errors by sending error Messages. |
2 | 0h | RW | Fatal Error Reporting Enable (FERE) This bit, in conjunction with other bits, controls sending ERR_FATAL Messages Not supported. This bit is not connected to any logic |
1 | 0h | RW | Non-Fatal Error Reporting Enable (NERE) This bit, in conjunction with other bits, controls sending ERR_NONFATAL Messages. |
0 | 0h | RW | Correctable Error Reporting Enable (CERE) This bit, in conjunction with other bits, controls sending ERR_COR Messages. |