Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Power Management Data, Control/Status Register Bridge Support Extensions, Control And Status (IDE_HOST_PMD_PMCSRBSE_PMCSR) – Offset 54
This register contains the power management data, control and status register bridge support extensions, control and status registers.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0h | RO | Data (DATA) Not implemented. Hardwired to 0. |
23:16 | 0h | RO | Control/Status Register Bridge Support Extensions (CSRBSE) Not implemented. Hardwired to 0. |
15 | 0h | RO | PME Status (PMESTS) This bit is set when the function would normally assert the PME signal independent of the state of the PME_En bit. |
14:13 | 0h | RO | Data Scale (DS) Not implemented. Hardwired to 0. |
12:9 | 0h | RO | Data Select (DSEL) Not implemented. Hardwired to 0. |
8 | 0h | RO | PME Enable (PMEEN) A 1 enables the function to assert PME. When 0, PME assertion is disabled. |
7:4 | 0h | RO | Reserved |
3 | 1h | RO | No Soft Reset (NSR) When set to 1, this bit indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits. |
2 | 0h | RO | Reserved |
1:0 | 0h | RW | Power State (PWRST) This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below: |