Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
DEVIDLE Control (HECI1_DEVIDLEC) – Offset 800
This register allows host to configure the power mode
using D0i0/D0i3 support.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:3 | 0h | RO | Reserved |
2 | 0h | RW | DevIdle (DEVIDLE) SW sets this bit to 1'b1 to move the function into the DevIdle state. Writing this bit to 1'b0 will return the function to the fully active D0 state (D0i0). |
1 | 0h | RW | Interrupt Request (IR) SW sets this bit to 1'b1 to ask for an interrupt to be generated on completion of the command. |
0 | 0h | RO/V | Command-in-Progress (CIP) HW sets this bit on a 1'b1->1'b0 or 1'b0->1'b1 transition of DEVIDLE. While set, the other bits in this register are not valid and it is not allowed for SW to write to any bit in this register. |