Intel® Core™ Ultra Processors for H-series and U-series Platforms SOC I/O Registers
Port 1 Serial ATA Status (PxSSTS1) – Offset 1a8
Same definition as PxSSTS0.
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:12 | 0h | RO | RSVD0 (RSVD0) Reserved |
11:8 | 0h | RO/V | Interface Power Management (IPM) Indicates the current interface state. This field reflects the interface power management state for both device and host initiated power management. If an Automatic Partial to Slumber Transition occurs, PxSSTS.IPM shall reflect that the host has entered Slumber (PxSSTS.IPM = 6h). |
7:4 | 0h | RO/V | Current Interface Speed (SPD) Indicates the negotiated interface communication speed. |
3:0 | 0h | RO/V | Device Detection (DET) Indicates the interface device detection and Phy state. While the true reset default value of this register is 0h, the value read from this register depends on drive presence and the point in time within the initialization process when the register is read. The means by which the implementation determines device presence may be vendor specific. However, device presence shall always be indicated anytime a COMINIT signal is received. |